A silicon integrated system or System on a Chip (SoC) includes at least a central processing unit (CPU) on which programs can be run, a direct memory access controller (DMA controller), a memory and a memory management unit. Such SoCs are typically included in electronic devices such as general purpose computers, decoder units or “Set-Top-Boxes”, personal digital assistants or PDAs, mobile phones, etc.
In physical memory, a variable size memory space is dynamically allocated to each application program or user program. More specifically, each user program has access to only some of the pages of physical memory. These pages form a memory space (which may be discontinuous) which is addressed at memory bus level by physical addresses, but which is known to the user program via an address space (normally continuous) called a virtual address space which the program accesses with virtual addresses. The virtual address space is specific to the user program. The relationship that links the virtual addresses in the address space and the physical addresses in physical memory is stored in the form of a translation table, called a page table, which is managed by the operating system and stored in main memory. The latest address translations computed by the MMU table reloading unit are stored in a specific cache memory called a TLB (Translation Look-aside Buffer).
Each entry of the TLB, that is each line corresponding to a translation in the TLB, comprises an address space identifier (ASID) to distinguish identical virtual addresses in different address spaces. Each ASID is linked, on a one-to-one basis, to a predefined address space of the system.
The DMA controller performs data transfers between the internal memory of the SoC and peripheral memory devices (for example, disks) based on information supplied to it. This information comprises the source physical address of the transfer, the destination physical address of the transfer and the size of the memory area to be transferred.
Conventionally, a program requesting programming of the DMA controller for a DMA transfer running on the SoC in user mode (also called application mode or non-privileged mode) supplies a virtual address, which is the virtual address of the source of the DMA transfer or the destination of the DMA transfer, to the operating system or OS. The OS, running in privileged mode (also called supervisor mode or kernel mode) then takes control, translates the supplied virtual address into a corresponding physical address. It requires in turn storage of the source physical address of the transfer obtained in the source register, storage of the destination address in the destination register and storage of the size in the size register, and this from the virtual address of the registers. The OS then supervises the transfer performed by the DMA controller based on the information stored in its registers and notifies the program initiating the request of the result of the transfer.
The store instructions normally used are of the type: “STORE pa_src@dma_src_reg_adr”, “STORE pa_dest@dma_dest_reg_adr” and “STORE size@dma_size_reg_adr”, in which “pa_src” is the source physical address, “pa_dest” is the destination physical address, “size” is the size of the memory area transferred, “dma_src_reg_adr”, “dma_dest_reg_adr” and “dma_size_reg_adr” are respectively the virtual addresses of the source, destination and size registers. The first instruction above in plain language means “store the data corresponding to the source physical address “pa_src” in the source address register of the DMA controller whose virtual address is “dma_src_reg_adr””. This instruction therefore supplies a virtual address argument “dma_src_reg_adr” and a data argument “pa_src” to be stored at the address supplied as an address argument.
With reference to FIG. 1 which shows an example of a conventional SoC, the conventional programming path for the DMA controller is as follows: the virtual address “dma_src_reg_adr” is supplied by the CPU to the MMU over the virtual address bus VA. The MMU translates it into a physical address, checks the rights of access to this physical address, then applies it to the physical address bus PA, via which it is made available in particular to the DMA controller on the general bus A which is linked to a set of entities comprising, for example, disk controllers, physical memory, etc.
In parallel, the source physical address “pa_src” is applied by the CPU to the data bus DAT, from which it is made available on the general data bus D, also linked to the set of entities.
The source address and the address of the source register are respectively applied to the general data bus D and to the general address bus A according to the protocol adopted for bus management. According to the bus management protocols, the physical address of the source register is applied, for example, to the general address bus A virtually at the same time as the source physical address “pa_src” is applied to the general data bus D, or the address of the source register is positioned on the general address bus A one clock pulse before the source physical address is positioned on the general data bus D (for a protocol in which the addresses are positioned one clock pulse before the corresponding data), or even one of the addresses is applied on the rising edge whereas the other is applied on the falling edge, and so on.
The translation is performed by the MMU using a translation table.
A number of attempts have recently been made to program the DMA controller directly by a program running in user mode, instead of by the OS. This stems in particular from the very high proportion of time required for the programming of a DMA controller by the OS, compared to the data transfer time itself that is achieved by the DMA controller.
One of the difficulties encountered originates from the fact that the registers of the DMA controller must be programmed with physical addresses, whereas the programs in user mode do not have access to them and it is not desirable, particularly for security reasons, for them to have access to them.
Solutions are proposed in the documents “User-Level DMA without Operating System Kernel Modification”, by Evangelos P. Markatos and Manolis G. H. Katevenis (Institute of Computer Science, Science and Technology Park of Crete, 1997 IEEE), “Protected User-Level DMA for the Shrimp Network Interface”, by M. A. Blumrich et al. (Proc of the 2nd International Symposium on High Performance Computer Architecture, pages 154-165, February 1996) and “Integration of Message Passing and Shared Memory in the Stanford Flash Multi-Processor”, by J. Heinlein et al. (Proc. of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 38-50, 1994).
According to these solutions, the user program executes an already existing store instruction of the “STORE” type of instruction described above, but places as the address argument the source or destination virtual address that it wants to program in the DMA controller, and not the address of the register of the DMA controller to be programmed. The effect of this is to force the MMU to translate the source or destination virtual address supplied into a corresponding physical address. This technique also enables the MMU to check that the user program does indeed have the right to access this address.
Two additional difficulties had to be taken into account. First of all, it is essential to ensure that the DMA controller receives this physical address which is located on the address bus A, and writes it as data into its source or destination register. Moreover, it is also essential to allow the memory area to which the physical address applied to the bus corresponds, to disregard the STORE instruction because this instruction is not addressed to it.
The above-mentioned document provides a solution to these problems. This solution consists in setting to 1 the most significant bit (MSB) of the source or destination address of a DMA transfer before it is supplied to the MMU. Thus, the DMA controller receives, using its appropriate state machine, as data to be stored in one of its registers, any word including an MSB at 1.
This solution therefore performs implicit addressing (or shadow addressing), based on the “STORE” instruction and the prefix 1.
The drawback of this technique is that the system must not include any memory area or peripheral device with an address beginning with 1, which halves the addressable memory space that is actually available. Thus, for a 32-bit (or 4 GB) system, the addressable memory space in practice is reduced by half, to 231 bits (or 2 GB), which is very detrimental.